This invention relates to the testing of electrical circuits, and more particularly to a means for simultaneously testing a multiplicity of circuits for an open, intermittent open or high resistance condition as they are subjected to temperature cycling, vibration, or other demanding environmental conditions.
Integrated circuits, first developed for use in computing equipment, have since been employed in a wide variety of products not previously associated with data processing or computing, for example in automobiles and household appliances. This widespread usage springs from some substantial advantages afforded by integrated circuits as compared to prior electrical circuitry, e.g. smaller size, lower cost and increased reliability. However, as the demand continues for increasingly complex integrated circuits formed on ever smaller semiconductor chips, a corresponding need arises for equipment and processes to test the circuitry to ensure its reliability.
Arrangements for testing integrated circuits are known in the art. For example, U.S. Pat. No. 3,783,372 (Boyd) discloses a high gain operational amplifier for a hand-held testing device, which generates a relatively low reference output current when its input is connected to an open circuit, but generates a substantially higher amperage output when connected to a short circuit. U.S. Pat. No. 3,792,349 (Bobbitt) discloses a network for detecting circuit discontinuities utilizing either steady-state voltages or pulses, having both positive and negative potentials. Upper and lower channels of the device each employ relays in connection with a diode gate, a biased amplifier, a comparator and a pair of NAND gates.
A sequential tester for finding electrical shorts is disclosed in U.S. Pat. No. 4,115,731 (Axtell). In the course of testing, a user touches two probes of the test apparatus to the conductive strips of a printed circuit board. When both probes are on the path of the short circuit, the probe assembly indicates this to the operator. A mechanical approach to parallel testing of multiple circuits is shown in U.S. Pat. No. 4,471,298 (Frohlich). Two parallel bars, each with set of probe contacts, are movable relative to a printed circuit board in the direction perpendicular to their extension. Test voltages are sequentially applied to selected pairs of probe contacts.
While such approaches are satisfactory in many respects, they fail to address the needs of integrated circuits fabricated for use in certain particularly demanding environments, for example aviation, space exploration and certain military applications, where circuitry can be highly complex, yet reliability of each circuit is paramount. Such circuits often are subjected to stressful environmental conditions, for example extreme temperature cycling or vibration. Any system for testing such circuitry must involve a reasonable approximation of the environmental conditions or stress anticipated during use, and be capable of detecting not only permanently open circuits, but also circuits which are intermittently open, or circuits which, while not totally open, experience an unacceptable increase in resistance or impedance, whether permanently or intermittently.
Sequential testing equipment, even if automated, cannot meet these standards, as the time any given circuit is under test often is less than the time it is not by an order of magnitude or more. Intermittent unacceptable conditions can be completely overlooked by such a testing system.
Therefore, it is an object of the present invention to provide a system for the simultaneous or parallel testing of multiple circuits in an integrated circuit configuration, such as a single semiconductor chip or an assembly of integrated circuit packages connected to a printed circuit board.
Another object of the invention is to provide a means for identifying intermittent open conditions in tested circuitry, or intermittent conditions of unacceptably high resistance in a given circuit.
Another object is to provide a simple, low cost testing apparatus for rapidly identifying and displaying open or otherwise unacceptable conditions for one or more of a multiplicity of circuits.
Yet another object is to provide a system for parallel testing of integrated circuit packages and their multiple terminations to a printed circuit board, in which the recording of test results is triggered by a sensed error condition in one or more of the circuits.